1. Field of the Invention
The present invention relates to memories comprising an array of memory cell rows and columns formed on a substrate of silicon-on-insulator (SOI) type.
2. Discussion of the Related Art
FIG. 1 schematically shows a cell of a static memory of random access type (SRAM) of conventional structure with six transistors, called a 6T cell. The memory cell comprises inverters 1, 2, connected in antiparallel. The respective inputs of inverters 1, 2 are connected to respective bit lines BL, {overscore (BL)} via switches 3, controlled by a row selection signal carried by a word line WL. Each inverter 1, 2, is supplied by a high voltage VDD and a low voltage GND, currently the ground.
To write information into the memory cell, a voltage VDD is applied on one of bit lines BL, {overscore (BL)} and a voltage GND is applied on the other. Then, switches 3 are turned on to set the states of the inputs and outputs of inverters 1 and 2. Switches 3 are then turned off and the state of the signals across inverters 1 and 2 is maintained.
To read an information from the memory cell, each of bit lines BL and {overscore (BL)} is precharged to a voltage ranging between voltages VDD and GND, then switches 3 are turned on so that the voltages on the bit lines vary according to the state of the signals across inverters 1 and 2. A sense amplifier (not shown) connected to the bit lines provides a binary information in relation with the information kept in the memory cell.
Inverter 1 comprises a P-channel MOS transistor PI1 in series with an N-channel MOS transistor NI1. The source of transistor PI1 is connected to voltage VDD and the source of transistor NI1 is connected to voltage GND. The drains of transistors PI1 and NI1 are interconnected at a point O2. The gates of transistors PI1 and NI1 are interconnected at a point O1. Similarly, inverter 2 comprises transistors PI2 and NI2 connected like transistors PI1 and NI1, the gates of transistors PI2 and NI2 being connected to terminal O2 and the common drains of transistors PI2 and NI2 being interconnected at terminal O1. Switches 3 are formed of MOS transistors M1 and M2, generally with N channels.
FIG. 2 shows a row of a conventional SRAM. Six 6T memory cells MC0 to MC5 have been shown. Conventionally, to a memory cell row corresponds a single word line WL0 and to a memory cell column correspond two bit lines (BLj and {overscore (BLj)}, j ranging from 0 to 5). In such a memory, upon writing or reading of data in a memory cell, it is necessary to select, with word line WL0, all the memory cells in the row to which the searched memory cell belongs. This results in a high electric consumption.
To decrease the consumption, it is desired to reduce the number of memory cells activated upon access to the memory. A possibility consists of using several word lines per memory cell row, knowing that each word line activates a subset of memory cells of the row. This type of so-called “multiline” architecture thus requires having metal tracks corresponding to the different word lines run over the memory cells. By reducing the number of selected memory cells at each write and/or read operation, the memory consumption is decreased.
FIG. 3 shows a row of an example of embodiment of a “multiline” SRAM for which two word lines WL0, WL1 are associated with each row. Six 6T memory cells MC0′ to MC5′ have been shown. Each word line WL0, WL1 is connected to one memory cell out of two. On each read/write operation, only half of the memory cells in the row are thus selected.
It is also desired to obtain a memory for which the read and write operations may be performed at a high frequency. For this purpose, it is desired to reduce the bit line capacitance by decreasing the memory cell height.
Further, it is generally desired to decrease the general surface area of the memory cells.
However, in the case where a “multiline” memory is desired to be formed, it is often difficult to form a memory cell with a small surface area, and in particular with a small height.
To illustrate such a difficulty, a conventional example of a topology of 6T memory cell MC0 of FIG. 2 has been shown in FIG. 4, and a conventional example of topology of 6T memory cell MC0′ of the memory of FIG. 3 has been shown in FIG. 5.
FIG. 4 schematically shows memory cell MC0 of FIG. 2 in which the electric circuit of FIG. 1 is formed by a technology with one polysilicon level and three metallization levels formed on an SOI substrate. Other polysilicon and metallization levels may be present and used.
The surfaces delimited by a thin line correspond to active areas of the semiconductor substrate or to polysilicon strips deposited on the substrate and corresponding to MOS transistor gates. Although the view is not shown to scale, the relative dimensions and positions of each region are kept to show the real bulk of the integrated circuit. The double lines correspond to level-one metal strips. The thick horizontal black lines correspond to level-two metal strips, and the thick vertical black lines correspond to level-three metal strips. The crosses represent contacts connecting, through the insulating layers located between the metallization levels and the polysilicon level, metal strips to active areas or to polysilicon strips or vias connecting, through the insulating layers located between the metallization levels, metal strips to other metal strips. For clarity, the metal strips are not shown with surface areas proportional to the surface areas of the active areas. However, the position of each line is in accordance with the real position of the corresponding metal strip in the integrated circuit.
An active area 11 corresponds to MOS transistor A1, to MOS transistor N1, and to the connection between these transistors. An active area 12 corresponds to MOS transistor A2, to MOS transistor N2, and to the connection between these transistors. Active areas 13, 14 respectively correspond to MOS transistors P1, P2. Gates GN1, GP1 of respective MOS transistors N1, P1 correspond to portions of a polysilicon strip 16. Gates GP2, GN2 of respective MOS transistors P2, N2 correspond to portions of a polysilicon strip 18. Gates GA1, GA2 of MOS transistors A1, A2 correspond to respective portions of polysilicon strips 19, 20.
The different metal tracks of level one, two, and three are used to connect active areas 11, 12, 13, 14 and polysilicon strips 16, 18, 19, 20 to obtain an electric diagram equivalent to the diagram shown in FIG. 1. In particular, word line WL0 connected to gates GA1, GA2 of transistors A1, A2 corresponds in the present example to a level-two horizontal metal strip and supply lines GND, VDD and bit lines BL0, {overscore (BL0)} correspond to level-three vertical metal strips.
To reduce the memory cell surface area, the contacts, vias, and metal portions ensuring the connection between gates GA1, GA2 of transistors A1, A2 and word line WL0 are arranged at the level of the vertical edges of the same row on either side of the shown cell.
FIG. 5 shows an example of embodiment of memory cell MC0′ of the “multiline” memory of FIG. 3 which keeps a topology similar to that of FIG. 4 as for the transistor arrangement. For two adjacent cells of a same row, gates GA1, GA2 of transistors A1, A2 are connected to different word lines WL0, WL1. The contacts, vias, and metal portions ensuring the connection of gates GA1, GA2 to word lines WL0, WL1 thus cannot be shared between two adjacent memory cells and must thus be placed within the cell.
To be able to connect the two gates GA1, GA2 of transistors A1 and A2 to one or the other of word lines WL0, WL1, it is necessary to provide two vertical metal tracks 23, 24, respectively connected to gates GA1, GA2 of transistors A1, A2 and to one of word lines WL0, WL1. Given the bulk of the first metallization level, metal tracks 23, 24 are formed in the second metallization level. Word lines WL0, WL1 thus correspond to level-three metal strips, and supply lines GND, VDD and bit lines BL0, {overscore (BL0)} correspond to level-two metal strips.
The displacement of the contacts, vias, and metal portions ensuring the contact of gates GA1, GA2 of transistors A1, A2 to the inside of the memory cell requires increasing the memory cell height due to the bulk of the first metallization level. Further, the presence of tracks 23, 24 at the same metallization level as bit lines BL0, {overscore (BL0)} and supply lines GND, VDD requires increasing the memory cell width.
In a manufacturing technology in which the smallest pattern has a 0.13-μm length, a 2.80-μm width ΔX, a 1.10-μm height ΔY, and a 3.08-μm2 surface area may be obtained for the memory cell of FIG. 4. As a comparison, the memory cell of FIG. 5 has a 2.56-μm width ΔX, a 1.54-μm height ΔY, and a 3.9424-μm2 surface area. A 40% increase in the height and a 22% increase in the surface area are thus obtained. The capacitances of bit lines BL0, {overscore (BL0)} of the “multiline” memory of FIG. 5 are thus increased with respect to those of the memory of FIG. 4. Performances in terms of read/write frequency are thus reduced.